1. Field of the Invention
The present invention relates to the bonding of semiconductor III-V photonic wafers and CMOS electronics wafers in order to realize solid state light devices in which light and electrical signals are transferred between the bonded wafers.
2. Prior Art
The advent of 3D-IC and solid state light technologies is making it possible to integrate arrays of light emitters or detectors patterned from III-V material and bonded to a CMOS control circuit (see U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902, as well as G. Y. Fan, et al, III-nitride micro-emitter arrays: development and applications, J. Phys D: Appl. Phys. 41 (2008), Z. Gong, et al, Efficient flip-chip InGaN micro-pixellated light-emitting diode arrays: promising candidates for micro-displays and colour conversion, J. Phys D: Appl. Phys. 41 (2008), and H. Schneider, et al, Dual band QWIP focal plane array for the second and third atmospheric windows, Infrared Physics & Technology, 47 (2005) 53-58). In particular, recent advances in 3-dimensional integrated circuits (3D-IC) are making it possible to integrate multi-layer optoelectronics devices comprising relatively high resolution arrays of light emitters (see U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902, as well as G. Y. Fan, et al, III-nitride micro-emitter arrays: development and applications, J. Phys D: Appl. Phys. 41 (2008) and Z. Gong, et al, Efficient flip-chip InGaN micro-pixellated light-emitting diode arrays: promising candidates for micro-displays and colour conversion, J. Phys D: Appl. Phys. 41 (2008)) or light detectors (see H. Schneider, et al, Dual band QWIP focal plane array for the second and third atmospheric windows, Infrared Physics & Technology, 47 (2005) 53-58) (collectively referred to as “photonic” arrays). Evidence of such trend are the devices described in G. Y. Fan, et al, III-nitride micro-emitter arrays: development and applications, J. Phys D: Appl. Phys. (2008) which are micro-LED array devices comprising single wavelength device pixels patterned on III-V compound semiconductor layers such as GaN driven passively and packaged in a PGA package using wire-bonding. In G. Y. Fan et al., hybrid integration of the III-V emitter array with a silicon control IC using flip-chip bonding is used. Similar light emitter array devices of single color 8×8, 16×16 and 64×64 pixels are fabricated and integrated with CMOS using flip-chip bonding (see G. Y. Fan, et al, III-nitride micro-emitter arrays: development and applications, J. Phys D: Appl. Phys. 41 (2008) and Z. Gong, et al, Efficient flip-chip InGaN micro-pixellated light-emitting diode arrays: promising candidates for micro-displays and colour conversion, J. Phys D: Appl. Phys. 41 (2008)). These types of micro-emitter array devices can use flip-chip and wire bonding techniques because their photonic elements (pixels) size are relatively large (a few hundred microns) which result in low electrical interconnect density that make it possible to use such techniques for bonding the III-V light emitting array to the control CMOS.
Of particular interest is the ultra high pixel density emissive micro-display device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902. These types of devices are typically an array of micro dimensional solid state light emitting elements that are formed from one type of photonic materials, such as III-V material, and integrated using 3D-IC techniques to a micro electronic circuit array that is used for coupling electrical signals in and out of the photonic array (see U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902, as well as G. Y. Fan, et al, III-nitride micro-emitter arrays: development and applications, J. Phys D: Appl. Phys. 41 (2008), Z. Gong, et al, Efficient flip-chip InGaN micro-pixellated light-emitting diode arrays: promising candidates for micro-displays and colour conversion, J. Phys D: Appl. Phys. 41 (2008), and H. Schneider, et al, Dual band QWIP focal plane array for the second and third atmospheric windows, Infrared Physics & Technology, 47 (2005) 53-58). For the majority of these types of devices, wafers of the photonic material from which the photonic array elements are formed are typically bonded to a micro circuit array wafer, using one or more of the wafer bonding techniques such as those described in M. Alexe and U. Güsele, Wafer Bonding Applications and Technology, pp 327-415, Springer 2004 and Q. Y. Tong and U. Güsele, Semiconductor Wafer Bonding Science and Technology, pp 203-261, Wiley 1999, with the electrical signals being transferred between the bonded photonic and electronics wafers using electrical interconnect via array such as that described in M. Alexe and U. Güsele, pp. 177-184. The wafer bonding interface surface required in the fabrication of these types of devices would therefore involve embedding an array of electrical vias within the bonding interface surface between the photonic and electronic wafers. Furthermore, when the elements of photonic array and its associated electronic circuit elements are micro dimensional in size (i.e., few microns in size such as with the case of the device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902), the density of the interconnect vias across the bonding interface can reach more than one million interconnect vias per square centimeter.
Wafer bonding for these types of devices would also include means of achieving adhesion (bonding) across the wafer bonding interface surface including the cross section of the interconnect vias as well. The bonding across the major part of the wafer interface surface is typically achieved using an intermediary layer that can be fused across the interface surfaces. For the type of device mentioned earlier, wafer bonding is achieved through fusion bonding of a highly polished intermediary layer across the bonding interface of the wafers that can be accomplished either at room temperature (see U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944) or at elevated temperature and pressure conditions (see M. Alexe and U. Güsele, Wafer Bonding Applications and Technology, pp 327-415, Springer 2004 and Q. Y. Tong and U. Güsele, Semiconductor Wafer Bonding Science and Technology, pp 203-261, Wiley 1999). For the metal interconnects, via to via solid-state diffusion bonding across the bonding surface is typically achieved by interfusion of the vias cross sections which includes the use of elevated temperature annealing of the bonded wafers which leverages the strength of the bonding across the interface surface achieved by the fused intermediary layers and the elevated temperature of the annealing to create the thermal compression conditions needed to interfuse the electrical interconnect vias across the bonding surface of the two wafers (see U.S. Pat. No. 7,622,324 and M. Alexe and U. Güsele, Wafer Bonding Applications and Technology, pp 327-415, Springer 2004).
U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 describe an emissive micro-display device that is comprised of multiple layers of patterned solid state light emitting material which are bonded into a stack and are collectively bonded to a CMOS micro electronic circuit array. The bonded stack of patterned solid state light emitting material form an array of multi-color light emitting pixels that is controlled by a CMOS micro electronic circuit layer to which the stack of patterned and bonded solid state light emitting material is bonded. The realization of device structures such as that described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 requires bonding of photonic to photonic wafers as well as bonding of silicon (Si) based CMOS to photonic wafers that include the transfer of both electrical as well as light signals across the bonding surfaces of the bonded semiconductor wafers. No prior art reference was found that describes methods for the bonding semiconductor wafers that incorporate the transfer of both electrical and light signals across the bonded wafer interface.
FIGS. 1A-1D are illustrations of typical prior art semiconductor wafer bonding techniques including direct fusion bonding (FIG. 1A), aligned fusion bonding (FIG. 1B), eutectic bonding (FIG. 1C), BenzoCycloButene (BCB) polymer adhesive bonding (FIG. 1D). Of particular interest is FIG. 1B which illustrates the aligned fusion bonding of wafers that incorporate electrical interconnect vias across the bonding surface described in the prior art (see U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944, as well as M. Alexe and U. Güsele, Wafer Bonding Applications and Technology, pp 327-415, Springer 2004 and Q. Y. Tong and U. Güsele, Semiconductor Wafer Bonding Science and Technology, pp 203-261, Wiley 1999). In this wafer bonding technique prior to bonding of the two wafers, which are typically silicon (Si) based, alignment marks are included within each wafer having sufficient feature definition to enable precise alignment of the two wafers to less that 10% of the diameter of the interconnect vias. Prior to bonding, each of the two wafers are separately planarized using chemical mechanical bonding (CMP) techniques. An intermediate bonding layer typically of dielectric material, which is typically silicon oxide (SiO2), is deposited on the planarized surface of the two wafers separately. Interconnect metal via posts are then formed on the bonding surface of the each of the two wafers typically using a single electrically conductive metal such as nickel. The formed bonding interface surface is then polished using CMP to within less than half nanometer of roughness, surface activated and the wafers are then aligned using the incorporated alignment marks with their bonding interface surface facing each other and brought into contact. Appropriate levels of pressure and elevated temperature are applied to increase the bonding strength across the bonding surface of the two wafers. Depending on the surface roughness achieved on the bonding interface surface, at the end of this process the dielectric intermediary layers deposited on the surface of each of the two wafers will fuse together across the wafers bonding interface surface. However, the wafer polishing and surface activation processes could cause the interconnect vias interface surface to be recessed below the dielectric surface which would result in the presence of a gap between the opposing vias across the wafer bonding interface surface. The presence of such gaps between the interconnect vias could cause excessive level of electrical resistance between the corresponding electrical circuits of the bonding wafers. In order to minimize the electrical resistance across the interconnect vias, the bonded wafers are subjected to further annealing at elevated temperature to cause the aligned vias to expand and interfuse together across the bonding interface.
Several aspects of prior art bonding processes (see U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944) make it more effective for bonding wafers having substantially similar thermal expansion characteristics but substantially less effect for bonding wafers with differing thermal expansion characteristics, such as the case when a wafer made from III-V material and possibly grown on substrates such as sapphire needs to be bonded to a Si wafer. When the thermal expansion characteristics of the two wafers to be bonded are substantially different, excessive and prolonged elevated temperature annealing after the bonding intermediary layers of the respective wafers have been fused together as described in U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944 would be terminal to the bonded wafers and would likely cause the achieved bonding to fail causing de-bonding of the intermediary layers. This means that the prior art prior art bonding methods (see U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944) are not likely to be effective in the bonding of wafers having substantially dissimilar thermal expansion characteristics such as the case when a wafer made from III-V material needs to be bonded to a Si wafer such as described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902.
Fusion bonding (see M. Alexe and U. Güsele, Wafer Bonding Applications and Technology, pp 327-415, Springer 2004 and Q. Y. Tong and U. Güsele, Semiconductor Wafer Bonding Science and Technology, pp 203-261, Wiley 1999) in general and low temperature fusion bonding in particular (see Q. Y. Tong and U. Güsele, pp. 49-101 and U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944) of wafers requires pre-bonding planarization of the wafers to be bonded to a highly stringent level that can reach substantially less than one nanometer root mean square (RMS) across the wafer surface. However, wafers made from III-V material characteristically have a certain amount of bow that can be substantially higher than one micron across the wafer surface. Such an excessive level of wafer bow would make very difficult, if not practically impossible, to make use of the prior art wafer bonding methods described in U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944 for the bonding of a wafer made from III-V material to a Si wafer such as those described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 and H. Schneider, et al, Dual band QWIP focal plane array for the second and third atmospheric windows, Infrared Physics & Technology, 47 (2005) 53-58.
The emissive micro-display (imager) device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 represents the state of the art in emissive micro-displays and uses III-V compound semiconductor materials as emissive layers promising high brightness, power efficiency, multi-color, long lifetime and highly reliable micro-displays with color purity for use in a variety of applications including imaging, projection, and medical among other uses. The emissive device in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 is comprised of a large array (more than one million per square centimeter) of solid state light emitting pixels, either laser diodes (LDs) or light emitting diodes (LEDs), depending on current injection conditions, integrated onto a Si-based CMOS comprised of a reciprocating array of digital control logic circuits using 3D-IC technology. The array of digital control micro circuits of the imager device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 would typically be manufactured using standard Si-based CMOS technology whereby a multiplicity of digital control micro circuit arrays are formed as individual dies that covers the surface of a CMOS wafer. The emissive pixel array of the imager device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 would typically be manufactured by patterning a multiplicity of pixel arrays, that correspond with the dies of the CMOS wafer, onto the surface of a wafer made from III-V compound materials such as InGaN/sapphire or AlGaInP/GaAs, for example, depending on the required wavelength of the light to be emitted. The imager device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 would typically be manufactured by aligned bonding of the CMOS wafer, acting as a host wafer, and the patterned III-V wafer to ultimately create a wafer stack that is comprised of a multiplicity of device dies that covers the surface of the bonded wafer pair. As described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902, after the growth substrate of the III-V wafer is removed either by epitaxial lift-off (ELO) or laser lift-off (LLO) techniques, the resultant III-V/CMOS wafer stack would become the host wafer upon which a second and third patterned III-V wafer are sequentially bonded to ultimately create a stack of multiple patterned III-V layers bonded on the top of the CMOS wafer. The ultimate multi-color imager device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 would be comprised of multiple patterned (pixelated) III-V layers stacked on top of the CMOS control logic array making the device able to emit any combination of light with multiple wavelengths from each pixel under the control of its associated CMOS logic circuit.
A distinctive aspect of the multi-color imager device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 is that its operation requires electrical signals to be coupled from the CMOS logic circuit of each pixel to each of the individual solid state light emitting layers of the multi layer stack. Furthermore, for the multi-color light to be emitted from the top surface of that imager device, light would have to be coupled from the layer where it is generated through the stack of layers above it. As described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902, within each of the light generating layers of the stack, light would be propagated (coupled) through multiplicity of vertical waveguides that are distributed across each layer. Meaning that the multi-color imager device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 would, in addition to requiring that electrical signals be coupled through each of the individual light emitting layers of the multi layer stack, also require that light be coupled through each of the individual solid state light emitting layers of the multi layer stack and their respective bonding layers as well. This requirement would imply that the bonding of the light generating (photonic) wafers used in the fabrication of the multi-color imager device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 would have to incorporate means for the transfer of both electrical as well as light signals between the stacked layers that would form the ultimate multi-layer imager device. No prior art was found that describes wafer bonding that incorporates means of the bonding of multiple wafers that incorporate means for the transfer of light signals between the bonded wafers.
As explained earlier, the wafer bonding described in the prior art (see U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944) that incorporates electrical interconnect vias relies on the use of post fusion bonding elevated temperature annealing in order to interfuse the incorporated metal interconnect vias across the bonding surface of the bonded wafers. In order to close the gap between the surface of the interconnect vias at each wafer bonding surface that is formed mostly due to the uneven response of the via metal and intermediary dielectric layer to the pre-bonding wafer chemical mechanical planarization (CMP) and the bonding surface activation steps, the electrical interconnect vias must contain enough volumetric size of metal to allow the metal expansion at the elevated temperature of the annealing step to fill in the formed gap between the facing vias across the bonding surface of the wafers. Depending on the geometry of the formed electrical vias, that requirement would dictate that the interconnect vias be more than 1.5 micron in height and more than 3 micron in diameter. Such a height for the electrical interconnect vias would be of no critical consequence when only electrical signals need to be transferred across the wafer bonding interface. However, when the wafer bonding surface needs to transfer light in addition to electrical signals the situation becomes vastly different since the excessive height of the interconnect vias would consequently cause excessive thickness of the intermediary bonding layer between the two wafers which could cause undesired attenuation (through absorption) of the light being transferred between the bonded wafers (layers) especially since the resultant thickness of the bonding between the two wafers is double the thickness of the intermediary bonding layers formed at the bonding side of each of the two wafers. Therefore prior art wafer bonding (see U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944) that incorporates electrical interconnect vias in which the height of the electrical vias as a design parameter, and consequently the thickness of the bonding intermediary layer, does not take into account the adverse effects of the attenuation of light signal being transferred across the wafer bonding surface due to the resultant thickness of the intermediary bonding layers.
One of the most important virtues of the multi-color imager device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 is that it eliminates most of the inefficiencies associated with present day spatial light modulators used in typical displays, thus making it possible to generate sufficient brightness of multi-color light to the display viewer from a very small pixel having a typical size of (10×10) micron or smaller. An important aspect of the fabrication of the multi-color imager device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902, therefore, is achieving sufficiently small pixel size (pixel pitch˜10 micron or less) that would enable such device to cost effectively realize a multi-color emission that can be used for a multiplicity of applications. Translated into the wafer bonding requirement, this level of multi-color pixel pitch would require wafer bonding interconnect via array with a density in the range of 4 million vias per square centimeter or higher; meaning˜5 micron electrical interconnect via pitch or lower. No prior art exists that describes methods for wafer bonding at such ultra high interconnect density especially incorporating means for the transfer of both light and electrical signals transfer between the bonded wafers across the bonding layer.
The excessive diameter of the electrical interconnect vias in prior art wafer bonding methods (see U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944) would be of no critical consequences when the density of the electrical interconnects is well below 106/cm2 such as the case in many 3D-IC comprised of an electronics CMOS wafer being bonded to another electronics CMOS wafer. However, when the wafer bonding surface needs to incorporate multiple electrical vias for each few micron optical element (pixel) such as the case of the imager described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902, excessive electrical vias diameter become a determinant for achieving high density optical element (pixel) pitch. Therefore, prior art wafer bonding methods (see U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944) in which the diameter of the electrical interconnect vias as a design parameter, and consequently the achievable density of the interconnect vias, do not take into account the limitation such a parameter places on the pixel pitch that can be achieved when such wafer bonding methods are used in the bonding of the semiconductor wafers of ultra high optical element (pixel) density optoelectronics devices such as those described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902.
As stated earlier, the device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 requires electrical interconnect via density in excess of 4×106/cm2. The limitation of the existing prior art (see U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944 and M. Alexe and U. Güsele, Wafer Bonding Applications and Technology, pp 327-415, Springer 2004 and Q. Y. Tong and U. Güsele, Semiconductor Wafer Bonding Science and Technology, pp 203-261, Wiley 1999) is that at such a fine via pitch the amount of metal in the formed fine pitch interconnect via would not be sufficient to close the gap between the vias using post bonding elevated temperature annealing unless the via height and diameter, and consequently the intermediary bonding layers thickness is substantially increased to become significantly larger than 1.5 micron, which would result in interconnect vias having a fairly high aspect ratio (expressed in terms of the ratio of the via height to its diameter). As explained earlier, such an increase in the intermediary bonding layer thickness will become even more detrimental to the transfer of light signals between the bonded wafers for the case when light has to be transferred across the bonding interface. Furthermore, when the interconnect vias aspect ratio becomes too high, the expansion of the interconnect vias during the elevated temperature annealing step required to interfuse the interconnect vias across the wafer bonding surface could result in the creation of gaps along the interconnect via height that ultimately be detrimental to achieving the low electrical resistance critically needed to transfer electrical signal between the bonded layers.
In order to achieve multi-color and ultra high pixel density capabilities, the device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 is composed of multiple patterned III-V material based photonic layers, one for each primary color wavelength of interest, which are bonded to each other and to a Si CMOS wafer which has the required drive circuitry. Due to the ultra high pixel density sought after in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 and the resultant ultra high interconnect density, which can be higher than 4×106/cm2, bonding techniques such as flip-chip, conventional eutectic bonding and the like are not a feasible way to realize multi-color emissive micro-display device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902. Furthermore, due to the stacking of multiple light emitting layers to the control circuitry CMOS wafer, the emissive micro-display device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902 would require the transfer of both electrical signals as well as light between its constituent bonded layers. Prior art bonding methods such as those described in U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944, and M. Alexe and U. Güsele, Wafer Bonding Applications and Technology, pp 327-415, Springer 2004 and Q. Y. Tong and U. Güsele, Semiconductor Wafer Bonding Science and Technology, pp 203-261, Wiley 1999 are mostly suited for bonding silicon based wafers and as such suffer from severe deficiencies when used to bond wafers of dissimilar materials such as photonic wafers that are typically fabricated using III-V materials and control circuitry wafers that are typically fabricated using silicon (Si) based CMOS.
Three dimensional integrated circuits (3D-IC) with high density and multi-functional capability are recognized as the next revolution in the semiconductor device technology (see International Technology Roadmap for Semiconductors, www.itrs.net). To achieve 3D-IC integration, fabrication schemes based on chip-chip, chip-wafer or wafer-wafer bonding methods were recently developed (see U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944, and M. Alexe and U. Güsele, Wafer Bonding Applications and Technology, pp 327-415, Springer 2004 and Q. Y. Tong and U. Güsele, Semiconductor Wafer Bonding Science and Technology, pp 203-261, Wiley 1999). Of these different fabrication schemes, direct wafer-wafer bonding enables maximum throughput, and thus reduced cost. The important wafer level bonding techniques in use for 3D-IC integration are direct fusion bonding (FIG. 1A), aligned fusion bonding (FIG. 1B), eutectic bonding (FIG. 1C), and adhesion bonding (FIG. 1D) (see C-T. Ko, et al, Wafer-level bonding/stacking technology for 3D integration, Microelectronics Reliability 50 (2010) 481-488). Each of these wafer bonding technologies offers certain benefits and challenges. Among the technologies identified above, aligned fusion bonding is a viable bonding technique for the fabrication of the device described in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902. Direct and aligned fusion bonding (FIG. 1A & B) allow for wafer-to-wafer bonding utilizing bond formation between two dielectric layers on the respective wafers. Prior art U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944 describe aligned fusion bonding of silicon based wafers (primarily Si—Si or using SiO2—SiO2 bond formation) that incorporates only interconnect electrical vias to transfer electrical signals across the bonding interface of the bonded wafers. In addition, the electrical interconnect density that can be achieved by such wafer bonding techniques is limited to substantially less than one million electrical interconnects per square centimeter. In the vast amount of work on wafer bonding for 3D-IC integration (the various references cited in C-T. Ko, et al, Wafer-level bonding/stacking technology for 3D integration, Microelectronics Reliability 50 (2010) 481-488 and U.S. Pat. Nos. 7,622,324, 7,553,744, 7,485,968 and 7,387,944, none of the described wafer bonding techniques are suitable for the integration of the optoelectronic devices such as that conceived in U.S. Pat. Nos. 7,623,560, 7,767,479 and 7,829,902, in that these techniques do not include provisions for the transfer of both electrical and light signals across the bonded layers of an optoelectronic device that incorporates an array of ultra high density photonic elements (pixels).
Given the aforementioned drawbacks of current semiconductor wafer bonding methods when used for bonding semiconductor photonic III-V wafers and electronics CMOS wafers, overcoming such weaknesses is certain to have a significant commercial value especially in view of the growing demand for solid state light based displays. It is therefore an objective of this invention to provide semiconductor methods for bonding photonic III-V wafers to electronics CMOS wafers whereby the wafer bonding interface incorporates means for the transfer of both electrical as well as optical signals across the bonding interface. Said semiconductor wafer bonding methods will incorporate means to alleviate the detrimental effects on wafer bonding that could be caused by the mismatch in thermal expansion of III-V and conventional CMOS materials. Furthermore, said semiconductor wafer bonding methods will incorporate means to overcome the limiting effects the height and diameter of the electrical interconnect vias have on the performance of semiconductor optoelectronics devices fabricated using wafer bonding. Additional objectives and advantages of this invention will become apparent from the following detailed description of a preferred embodiment thereof that proceeds with reference to the accompanying drawings.